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xen/arm: Handle unimplemented VGICv3 registers as RAZ/WI
authorJeff Kubascik <jeff.kubascik@dornerworks.com>
Tue, 4 Feb 2020 19:51:50 +0000 (14:51 -0500)
committerJulien Grall <julien@xen.org>
Sat, 8 Feb 2020 12:06:19 +0000 (12:06 +0000)
commit69da7d5440c609c57c5bba9a73b91c62ba2852e6
treea3531849cb7ad227db894eb2f7f7307f1bb6d578tree | snapshot
parentcbd1a54f6dea3f4a7feed51e189ebae50ac9dd15commit | diff
xen/arm: Handle unimplemented VGICv3 registers as RAZ/WI

Per the ARM Generic Interrupt Controller Architecture Specification (ARM
IHI 0069E), reserved registers should generally be treated as RAZ/WI.
To simplify the VGICv3 design and improve guest compatibility, treat the
default case for GICD and GICR registers as read_as_zero/write_ignore.

Signed-off-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
Acked-by: Julien Grall <julien@xen.org>
xen/arch/arm/vgic-v3.c diff | blob | history
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